Samsung's Play: Owning the AI Memory Stack
The centerpiece of Samsung's SEMICON Taiwan presentation was HBM5, the successor to the HBM4E chips that Samsung and SK Hynix are currently shipping. Here's what Samsung is targeting:
| Metric | HBM4E (Current) | HBM5 (Target, ~2028) |
|---|---|---|
| Performance | Baseline | 2x |
| Perf per Watt | Baseline | +20% |
| Thermal Resistance | Baseline | -20% |
| Base Die Process | 4nm | 2nm (Samsung's own node) |
| Stack Options | 8-12 layers | 12, 16, 20 layers |
The 2nm base die is the standout detail. Moving the base die — the logic layer that sits at the bottom of every HBM stack — from 4nm to 2nm is a significant process shrink. It means more logic density, which enables more sophisticated memory controllers and wider interfaces without increasing the physical footprint.
But the real ambition is zHBM. Unlike traditional HBM, which sits next to the processor on a silicon interposer, zHBM stacks memory dies directly on top of the AI accelerator. Samsung's target: 8x the raw performance of HBM4E, 3x the performance per watt, and a 75-90% reduction in thermal resistance. Commercial launch is expected after 2029.
Jangseok Choi, Samsung's VP of memory product planning, also introduced the "CUBE" framework — Capacity, Utilization, Bandwidth, and Efficiency — as the organizing principle behind the company's memory roadmap. The idea is to move beyond single-metric improvements and optimize the entire memory subsystem as a unit.
Samsung also previewed zNAND-O, a next-generation NAND technology targeting 10x the bit density of DRAM and 7x the read bandwidth of conventional NAND, with sampling planned for 2028. The goal: DRAM-class speed at NAND-class capacity, tuned for the massive model sizes of future AI workloads.
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Meanwhile in Hefei: CXMT's First HBM3E
While Samsung was presenting its roadmap in Taiwan, CXMT was making its own history roughly 800 kilometers away in Hefei. The company has begun risk production of HBM3E — the first time a Chinese manufacturer has produced high-bandwidth memory at this level.
"HBM3E" might sound like a small step behind HBM4E, but in memory generations, the gap is real. SK Hynix began mass-producing HBM3E in 2024. Samsung and Micron followed. By 2026, both Korean leaders had moved to HBM4 production and were sampling HBM4E to customers with per-pin speeds of up to 16 Gbps.
CXMT's HBM3E, by the JEDEC standard, targets a 1,024-bit interface at 9.2 to 12.4 Gbps per pin, with standard configurations hitting 9.6 Gbps. That translates to roughly 1.2 TB/s of total bandwidth, with capacities of 24 GB (8-high stacks) or 36 GB (12-high stacks).
The company is not doing this alone. Alibaba's chip division T-Head and AI chipmaker Cambricon are already testing CXMT's HBM3E with their processors. Tencent has signed a long-term supply contract worth over 20 billion yuan (~$2.94 billion) over three to five years. ByteDance is also on the customer list.
CXMT plans to expand HBM3E production in 2027, and Chinese AI chip designers could begin using the memory in commercial products as early as next year if testing proceeds as planned.
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The Yield Question
If there's one number that explains both CXMT's progress and its constraints, it's yield.
CXMT's HBM3 production is reportedly achieving yields of around 25% for 8-high stacks. That means three out of every four chip stacks fail quality testing. For context, mature HBM production lines at Samsung and SK Hynix run at significantly higher yields — exact numbers are proprietary, but the difference is measured in multiples, not percentage points.
Low yields are expensive. Every failed stack represents wasted silicon, wasted processing time, and wasted capital. They also constrain volume: even if CXMT has the wafer capacity, a 25% yield means its effective output is a quarter of what the raw numbers suggest.
The root cause is well understood. CXMT lacks access to extreme ultraviolet (EUV) lithography machines, the cutting-edge tools made exclusively by Dutch firm ASML that enable the smallest, most efficient chip designs. US-led export controls have blocked Chinese chipmakers from acquiring EUV systems. CXMT relies on older deep ultraviolet (DUV) lithography, which requires more processing steps, produces larger feature sizes, and generally caps competitiveness against EUV-made chips.
Despite these constraints, CXMT has moved fast. The company built fab cleanrooms in 12 months — roughly half the time the rest of the semiconductor industry takes. It operates two major 12-inch fabs in Hefei and Beijing, with combined output of roughly 200,000 wafers per month, on track to hit 350,000 by the end of 2026. A Shanghai HBM packaging facility is expected to begin production by year-end.
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The Gap: Two Generations, But Shrinking
The generational math is clear: CXMT is entering HBM3E just as Samsung and SK Hynix are moving to HBM4E and planning HBM5. That's a two-generation gap.
But the generational framing doesn't tell the full story. Here's why:
First, the addressable market is segmented. Not every AI chip needs the absolute latest HBM. Inference chips, edge AI accelerators, and mid-range training processors can operate effectively with HBM3E-class bandwidth. For Chinese AI chipmakers who have been entirely locked out of advanced foreign HBM by US export controls — the US added advanced HBM to its China restrictions in December 2024 — even HBM3E at modest volumes is a qualitative improvement over having no domestic HBM source at all.
Second, the speed of CXMT's catch-up is accelerating. The company went from LPDDR5 (2023) to LPDDR5X (2025) to LPDDR6 (2026), closing the gap from two years to zero in mobile memory. Its DRAM revenue share grew from negligible to 7% globally in roughly three years, making it the fastest-growing DRAM supplier in Q2 2026, according to Counterpoint Research.
Third, the capital is there. CXMT's July 2026 IPO on the Shanghai STAR Market raised 57.9 billion yuan (~$8.6 billion), the largest in Asia this year. Of the planned proceeds, 13 billion yuan is earmarked for DRAM technology development and 9 billion for future-generation DRAM research. The company's H1 2026 revenue hit 150.3 billion yuan, up 874% year-on-year, with net profit of 77.6 billion yuan.
Neil Shah, Counterpoint's VP of research, summarized the outlook: CXMT's expanding capacity and fresh capital improve its prospects, but its HBM capability remains "unproven at scale."
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What to Watch
The memory story over the next two years will play out on two parallel tracks:
Track 1: Samsung and SK Hynix push the frontier. HBM5 with 2nm base dies, 20-layer stacks, and zHBM prototypes will define what's possible in AI memory. The competition between the two Korean giants — SK Hynix has been the early leader in HBM3E and HBM4, while Samsung is betting on a generational leap with HBM5 and zHBM — will determine the pace of innovation at the top of the market.
Track 2: CXMT builds the foundation. The immediate question is whether CXMT can move from risk production to commercial HBM3E volumes by 2027, and whether yields improve enough to make the economics work. The next question is whether it can repeat the pattern it showed in mobile DRAM — closing the gap faster than anyone expected — and push into HBM4 within a few years.
For now, the gap is real. But it's closing from both sides: Samsung is pulling ahead, and CXMT is catching up. The memory market that was a three-player game for decades now has a fourth player at the table — and it's not there to watch.
The Bigger Picture: China's Memory Ecosystem
CXMT's HBM push doesn't exist in isolation. It's part of a broader Chinese memory ecosystem that's maturing faster than many Western observers expected.
YMTC, China's leading NAND flash maker, is reportedly in talks with CXMT to jointly accelerate domestic HBM production. Qualcomm is exploring a collaboration with CXMT to develop custom DRAM for smartphones. Xiaomi has already committed to CXMT's LPDDR6 for its upcoming 18 Fold flagship. Lenovo, Honor, OPPO, and vivo are all on the customer list.
The ecosystem logic is straightforward: China has the world's largest smartphone market, a rapidly growing AI chip design sector, and a government that treats semiconductor self-sufficiency as a national priority. When all three align behind a domestic supplier, the supplier's growth trajectory stops looking like a startup's and starts looking like an industrial policy outcome.
The counterargument is equally straightforward: ambition and policy don't manufacture 2nm chips. EUV access remains blocked. Yields at 25% are not commercially viable at scale. And Samsung and SK Hynix are not standing still — they're accelerating.
Both arguments are true. The question is which one wins over the next five years. And based on CXMT's track record of closing generation gaps faster than expected, betting against Chinese memory is starting to look like a bet against history. The HBM race is no longer just a two-horse competition between Samsung and SK Hynix. It's now a four-player game, and the newest entrant has the backing of the world's largest semiconductor market, a freshly filled war chest from the biggest Asian IPO of the year, and a track record of moving faster than anyone predicted. The question isn't whether CXMT will matter in AI memory. It already does.