How SMIC Is Pushing the Boundaries of China's Semiconductor Self-Sufficiency

In July 2026, a Chinese state-backed enterprise launched volume production of homegrown 193-nanometer immersion DUV (Deep Ultraviolet) lithography machines—the most critical piece of equipment in semiconductor manufacturing. The news sent ASML's stock down more than 8% in a single day. For SMIC (Semiconductor Manufacturing International Corporation), China's largest chip foundry, it was validation of a strategy that many analysts had dismissed as impossible: producing advanced chips without access to EUV (Extreme Ultraviolet) lithography, the technology that TSMC and Samsung use to make the world's most advanced processors.

The Sanctions Paradox: How US Export Controls Accelerated SMIC's Progress

When the United States began restricting exports of advanced semiconductor equipment to China in 2022, the conventional wisdom was clear: without access to ASML's EUV lithography machines and the latest DUV immersion tools, Chinese foundries would be stuck at mature process nodes, unable to produce the advanced chips needed for AI, smartphones, and high-performance computing.

That prediction turned out to be wrong. By 2023, SMIC was producing 7nm-class chips for Huawei's Kirin 9000s smartphone processor. By 2024, it had refined the process to N+2. By 2026, its N+3 process achieved a transistor density of 113.4 million transistors per square millimeter (MTr/mm²)—slightly above TSMC's N6 node at 107.7 MTr/mm²—and a minimum metal pitch of 32.5 nanometers, tighter than some cells in Intel's 18A process.

All of this was achieved without a single EUV exposure. The secret: pushing DUV immersion lithography to its absolute physical limits through multi-patterning.

The N+1, N+2, N+3 Journey: SMIC's Alternative Process Roadmap

Rather than compete on conventional node names (7nm, 5nm, 3nm), SMIC developed its own internal naming system: N+1, N+2, and N+3. These aren't marketing labels—they represent successive generations of DUV-based process refinement, each pushing transistor density higher while managing the growing complexity of multi-patterning.

The N+3 achievement is particularly significant. Independent analysis by SemiAnalysis confirmed that the Kirin 9030 Pro's minimum metal pitch of 32.5nm is actually tighter than the ~36nm used in some high-performance cells of Intel's 18A (Panther Lake). However, this doesn't mean SMIC has caught up to Intel—Intel's 18A uses GAAFET transistors and backside power delivery, architectural advantages that go far beyond metal pitch. The comparison is a single metric, not a comprehensive benchmark.

The Economics: How Much Does DUV Multi-Patterning Actually Cost?

There's no free lunch in semiconductor manufacturing. SMIC's DUV-based approach to advanced nodes comes with significant economic penalties:

• Lower yields: Multi-patterning means each wafer goes through 4x more exposure and etching cycles per critical layer. More steps = more chances for defects. N+2 yields are estimated at 20-40%; N+3 yields remain challenging. For comparison, TSMC's EUV-based N5 yields exceeded 80% within a year of launch.
• Longer cycle times: A wafer that takes weeks to process at TSMC can take months at SMIC when using quad-patterning on multiple layers. This directly impacts revenue recognition and customer delivery timelines.
• Higher wafer costs: Third-party estimates suggest SMIC's 7nm-class wafers cost $8,000-$11,000 per wafer, potentially more expensive than TSMC's EUV-based N7. When you factor in lower yields, the cost per usable chip is even higher.
• Capacity constraints: SMIC's advanced node capacity (7nm and below) is estimated at ~45,000 wafers per month as of end-2025, with plans to expand to 60,000 by 2026 and 80,000 by 2027. TSMC's advanced node capacity is measured in hundreds of thousands of wafers per month.

But economics isn't the whole story. For Huawei, the question isn't "how much does this chip cost"—it's "can we get this chip at all?" When US sanctions cut off access to TSMC's advanced nodes, SMIC's DUV-based approach became the only viable path to producing advanced processors domestically. The premium is the price of independence.

The Homegrown DUV Breakthrough: July 2026

On July 28, 2026, the game changed. Shanghai Aishengna Electronic Technology Group, a state-backed enterprise, launched volume production of China's first domestically manufactured 193nm ArF immersion DUV lithography systems. The first customers: SMIC, Hua Hong Semiconductor, and CXMT (ChangXin Memory Technologies).

The development of these machines involved a multi-year collaboration across China's top research institutions: Shanghai Micro Electronics Equipment (SMEE) as the system integrator, specialized laser optics institutes in Shanghai for the deep ultraviolet light source, precision optical engineering teams in Changchun and Beijing for the projection lens assembly, and Tsinghua University for the dual-wafer positioning stage using magnetic levitation linear motors with sub-nanometer alignment precision.

This doesn't mean China has caught up to ASML. ASML's latest EUV systems remain unmatched, and Chinese DUV tools are likely a generation behind ASML's most advanced immersion DUV machines. But the breakthrough eliminates the single most critical dependency in China's semiconductor supply chain: the ability to manufacture lithography equipment domestically, immune to export controls.

The Big Fund III: $47.5 Billion Bet on Self-Sufficiency

Behind SMIC's progress is a massive financial commitment from the Chinese government. The National Integrated Circuit Industry Investment Fund—known as "Big Fund III"—was capitalized at 344 billion yuan ($47.5 billion). This follows Big Fund I (2014, 138.7 billion yuan) and Big Fund II (2019, 204 billion yuan), bringing total government semiconductor investment to over $100 billion across three phases.

The funding is not just for SMIC. It covers the entire semiconductor ecosystem: equipment manufacturers developing domestic lithography, etching, and deposition tools; chemical companies producing photoresists and specialty gases; EDA (Electronic Design Automation) software companies building domestic alternatives to Synopsys and Cadence; and advanced packaging foundries developing 3D chiplet stacking technologies.

The results are measurable. The equipment localization rate in new Chinese fabs has risen from less than 15% in 2020 to over 40% today. For mature process nodes (28nm and above), Chinese fabs are approaching 70-80% domestic tool self-sufficiency. The goal is not to match the world's best—it's to ensure that China's semiconductor industry can continue operating even under a complete technology blockade.

The Mature Node Dominance: China's Other Semiconductor Story

While the advanced node race captures headlines, China's real semiconductor strength is in mature process nodes—the 28nm, 45nm, and 65nm processes that power the majority of the world's chips. Automotive electronics, industrial controllers, IoT devices, power management ICs, and display drivers don't need 3nm transistors. They need reliable, cost-effective manufacturing at scale.

China is dominating this segment. SMIC's total monthly capacity reached 1.078 million wafers (8-inch equivalent) in Q1 2026, with capacity utilization at 93.1%. The company's Q1 2026 revenue hit $2.505 billion, up 11.5% year-on-year, with consumer electronics revenue up 27% and industrial/automotive revenue surging 63%.

According to industry data, China's share of global mature-node chip production was 34% in 2023 and is projected to reach 47% by 2027—making it the world's largest producer of mature-node chips. SEMI, the global semiconductor industry association, predicts that China's 300mm wafer fab capacity will reach 25% of the global total by 2026, with monthly capacity of 2.4 million wafers, surpassing South Korea as the world's largest.

The Export Surge: China Becomes a Chip Export Powerhouse

In the first half of 2026, China's integrated circuit exports reached $177.28 billion, a 96.1% year-on-year increase that nearly matched the entire year of 2025. In June alone, exports hit $38.21 billion, up 122.2% year-on-year—the fourth consecutive month of record highs. Semiconductors have now surpassed mobile phones as China's largest single export category.

The growth is driven primarily by price, not volume: export volume increased only 7%, while the average unit price surged 83.3%, with per-chip prices exceeding $1.20 in June. The global AI infrastructure buildout is driving demand for memory chips, where China's CXMT is becoming a significant player in the DRAM market.

Morgan Stanley projects that China's AI chip self-sufficiency rate—which rose from 10% in 2021 to 42% in 2025—will reach 49% by 2027, 59% by 2028, and 70% by 2030. This doesn't mean China will match the world's best chips. It means China will be able to supply most of its domestic AI computing needs with domestically produced chips—even if they're not the fastest or most efficient.

What SMIC Can't Do (Yet): The 3nm and Beyond Challenge

For all of SMIC's progress, the gap with TSMC and Samsung at the leading edge remains substantial. SMIC's N+3, at approximately 113.4 MTr/mm², is roughly equivalent to TSMC's N6 (2021) or early N5 (2020)—a 5-6 year gap in transistor density. In terms of performance and power efficiency, the gap is wider: independent analysis places the Kirin 9030's CPU cores at roughly Cortex-X2 IPC (Instructions Per Clock) level, about three years behind the best smartphone SoCs from Apple, Qualcomm, and MediaTek.

Looking ahead, the challenge intensifies:

The 3nm Wall

At 3nm and below, FinFET transistor structures reach their physical limits. The industry is transitioning to GAA (Gate-All-Around) transistors, which require fundamentally different manufacturing processes. SMIC has not publicly disclosed a GAA roadmap, though industry tracking suggests related platform development is underway.

The EUV Requirement

While DUV multi-patterning has carried SMIC to 5nm-class density, the path to 3nm and below becomes exponentially more difficult without EUV. The number of multi-patterning exposures required per layer would make the process economically unviable for anything beyond small-batch production. China's domestic EUV development is underway but remains years away from production-ready tools.

Yield Economics

Even if SMIC can technically produce 5nm chips, the question is whether it can do so at yields and costs that make economic sense. TSMC's N5 yields exceeded 80% within a year of launch. SMIC's N+3 yields are estimated at 20-40% after years of refinement. The gap in manufacturing maturity is not just about technology—it's about the accumulated experience of producing millions of wafers.

"Smaller node does not always mean better chip. Samsung's 5nm Snapdragon 888 and 4nm Snapdragon 8 Gen 1 were advanced on paper but plagued by heat and power issues. Real-world system performance is what matters." — Xie Zhifeng, SMIC Co-Founder, July 2026

The Geopolitical Chessboard: Rare Earths and Reciprocal Leverage

China's semiconductor strategy is not limited to chip manufacturing. The country has also deployed its dominance in critical materials as leverage. Since 2023, China has imposed export controls on rare earth elements, gallium, germanium, and graphite—materials essential for semiconductor manufacturing, permanent magnets, and advanced electronics.

In 2026, these controls have tightened further. China's exports of heavy rare earth oxides to Japan have effectively dropped to zero, straining Japan's production of high-end permanent magnets, precision motors, and industrial robots. The message is clear: if the US can restrict China's access to advanced chips, China can restrict the world's access to the materials needed to make those chips.

This is no longer a one-sided technology blockade. It's a mutual strategic entanglement—and both sides are feeling the cost.

Conclusion: The Foundry That Refused to Be Counted Out

SMIC's journey from being written off as "hopelessly behind" to producing 5nm-class chips without EUV is one of the most remarkable stories in the semiconductor industry. It's a story of engineering ingenuity under constraints, of massive government investment meeting relentless execution, and of a strategic bet that the laws of physics could be stretched further than most experts believed.

But it's also a story of trade-offs. SMIC's DUV-based approach is more expensive, slower, and lower-yielding than the EUV-based processes used by TSMC and Samsung. The gap between "can we make this chip" and "can we make this chip profitably at scale" remains wide. And the path to 3nm and below—where FinFET gives way to GAA and EUV becomes essential—presents challenges that even DUV multi-patterning cannot solve.

For the global semiconductor industry, SMIC's progress sends an unambiguous signal: the assumption that export controls would permanently lock China out of advanced chip manufacturing has been proven false. China can build advanced chips without Western equipment. It's more expensive, it's less efficient, and it's behind the leading edge—but it's real, it's scaling, and it's not going away.

For anyone watching the future of technology, geopolitics, and global supply chains, SMIC is the single most important company you need to understand.